A low-power bit-serial multiplier for finite fields GF(2m)
نویسنده
چکیده
This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF(2m) using a polynomial basis representation. Moreover, a low-voltage/low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a variety of binary fields up to an order of 2m. We detail that the bit-serial multiplier architecture can be implemented with only 28m gate equivalents, and that it is scalable, highly regular, and simple to design.
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